1. Field of the Invention
The present invention generally relates to semiconductor devices.
More specifically, the invention relates to vertical-gate MOS transistors.
2. Description of the Related Art
In the last years, the growing demand of higher and higher integration density of the semiconductor device has brought a reduction in size of the elements used in integrated circuits.
A basic integrated circuit element is the transistor; particularly, in high-density integrated circuits, field-effect transistors are used. The use of integrated transistors in a number of power applications, such as liquid crystal display drivers and the like, has made it necessary to manufacture small size transistors that are nevertheless able to withstand relatively high voltages (for example, 10V-70V). Limitations in the manufacturing of small size field-effect transistors (for example, of the MOS type) often arise from the length of the transistor channel, i.e., the region between the source and drain.
A well-defined channel length is important for the correct operation of the MOS transistor; in fact, many electrical characteristic parameters, such as the transconductance, depend on the transistor channel length.
Moreover, as the channel length becomes smaller, the correct operation of the transistor as a whole is impaired, due for example to short-channel effects, such as punch-through phenomena or a permanently short-circuited channel.
Moreover, as far as MOS transistors for relatively high power applications are concerned, further electrical characteristic parameters that make the manufacturing of a small size MOS transistor troublesome are the voltages that it can withstand at its PN junctions and gate oxide layer; in particular, in order to have the MOS transistor withstand the desired high voltages, these must be lower than the breakdown voltages of both the PN junctions and the gate oxide layer.
As known, the breakdown voltage of the PN junction depends on a certain number of design and manufacturing process parameters, such as the dopant concentration of the regions forming the PN junction and the width of such regions. Particularly, the lower the dopant concentration of the regions forming the PN junction the higher the breakdown voltage. Moreover, in case one or both of the regions forming the PN junction are lightly doped, the width of such regions must be enough to permit the extent of the depletion area in reverse bias condition, and this limits the possibility of reducing the integrated circuit area.
Likewise, the breakdown voltage of the gate oxide layer depends on a certain number of design and manufacturing process parameters, such as for example the thickness of such oxide layer. As known, the higher the thickness of the gate oxide layer the higher the voltage withstood by the MOS transistor. However, a higher thickness of the gate oxide layer reduces the saturation current of the MOS transistor. Thus, the thickness of such oxide layer should be kept relatively low, thereby reducing the voltages that can be withstood by the MOS transistor.
Vertical-gate MOS transistors (also known in the art as V-MOS, U-MOS, folded gate or trench gate transistors) are less affected by short channel effects. In these devices, a trench is formed in a substrate region of a chip of semiconductor material wherein the MOS transistor is integrated. The walls of the trench are covered with the gate oxide layer, and the trench is then filled with a conductive material (typically, a polycrystalline silicon layer) adapted to form the gate electrode (i.e., the trench gate). The source and drain regions of the MOS transistor are formed in the chip of semiconductor material at opposite sides of the trench.
This MOS transistor has a channel region developing along the vertical and bottom walls of the trench, between the source and drain regions. In such a way, even if the overall size of the vertical-gate MOS transistor is reduced, the channel region can be kept sufficiently long so as to prevent the short channel effects.
A vertical-gate MOS transistor is disclosed in the U.S. Pat. No. 4,455,740, which also describes a related manufacturing method.
The Applicants have observed that a vertical-gate MOS transistor realized according to the teachings of such patent is not able to withstand high voltages across the drain-substrate and source-substrate junctions, due to the fact that the drain and source regions are heavily doped (N+) diffusion layers.
The high dopant concentration of the drain and source regions reduces the source-substrate and drain-substrate junctions breakdown voltages, and thus the voltages that can be withstood by such PN junctions. Moreover, the gate oxide layer is not able to sustain high voltages, due to its thin thickness. Both these features make the prior art vertical-gate MOS transistor not particularly adapted for power applications.
The U.S. Pat. No. 6,586,800 proposes a different vertical-gate MOS transistor wherein the drain region consists of a layer buried in the chip of semiconductor material under the channel. The drain current is collected through a metallization formed at the bottom surface of the semiconductor material chip.
As an alternative to the bottom surface drain contact, a top-surface sinker adapted to collect the drain current may be provided, for example, as described in the U.S. Pat. No. 5,124,764.
In both the solutions, the dopant concentration of the drain region (but not of the source region) is chosen according to the desired breakdown voltage of the drain-substrate junction.
As a result, the breakdown voltages are relatively high for the drain-substrate junction, but low for the source-substrate junction. Thus, the proposed MOS transistor is inherently asymmetric; this may be a disadvantage, because in many applications (e.g., pass transistors used as switches) the source and drain regions should be interchangeable.
In any case, the thin gate oxide layer does not allow withstanding high voltages at the drain/source terminals of the MOS transistor.